CDCE72010 datasheet(49/70 Pages) TI

49 / 70 page

50W

VBB

VCXO_IN

AUX_IN

::VCXOBUFSEL

::VCXOACDCSEL

(AC=1,DC=0)

VCXOTERMSEL::

VCXOINVBB::

AUXINVBB::

50W

AUTOMATIC/MANUAL REFERENCE CLOCK SWITCHING (SMART MUX)

PRI_REF

SEC_REF

Internal

ReferenceClock

VCXOWith

100HzLoop

Auto-Reference

primary

secondary

primary

CDCE72010

www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008

Figure 17. VCXO_IN and AUX_IN Voltage Biasing Circuitry

The CDCE72010 supports two reference clock inputs, the primary clock input, PRI_REF, and the secondary

clock input, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selected

by the dedicated SPI register. In the manual mode the external REF_SEL signal selects one of the two input

clocks

In the automatic mode the primary clock is selected by default even if both clocks are available. In case the

primary clock is not available or fails, then the input switches to the secondary clock until the primary clock is

back. The figure below shows the automatic clock selection.

Figure 18. Automatic Clock Select Timing

In the automatic mode the frequencies of both clock signals has to be similar but may differ by up to 20%. There

is no limitation placed on the phase relationship between the two inputs.

The clock input circuitry is designed to suppress glitches during switching between the primary and secondary

clock in the manual and automatic mode. This insures that the clock outputs continue to clock reliably when a

transition from a clock input occurs.

The phase of the output clock will slowly follow the new input phase. The speed of this transition is determined

by the loop bandwidth. However, there is no phase build-out function supported (like in SONET/SDH

applications).

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