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CAT1021 데이터시트(PDF) 12 Page - Catalyst Semiconductor |
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CAT1021 데이터시트(HTML) 12 Page - Catalyst Semiconductor |
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12 / 21 page ![]() CAT1021, CAT1022, CAT1023 Doc. No. MD-3009 Rev. M 12 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1021/22/23 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION PIN (WP) The Write Protection feature (CAT1021 only) allows the user to protect against inadvertent memory array programming. If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT1021 will accept both slave and byte addre- sses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. READ OPERATIONS The READ operation for the CAT1021/22/23 is initiated in the same manner as the write operation with one exception, the R/W ¯¯ bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Figure 10. Immediate Address Read Timing SCL SDA 8TH BI T STOP NO ACK DATA OUT 89 SLAVE ADDRESS S A C K DATA N O A C K S T O P P BUS ACTIVIT Y: MASTER SDA LINE S T A R T |
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