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AD2437 데이터시트(PDF) 19 Page - Analog Devices |
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AD2437 데이터시트(HTML) 19 Page - Analog Devices |
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19 / 42 page ![]() Rev. 0 | Page 19 of 42 | July 2023 AD2437 Table 6. I2S/TDM Port—Target Timing IOVDD = 1.8 V IOVDD = 3.3 V Unit Parameter Min Max Min Max Timing Requirements tBCLKW BCLK Width 19.5 9.5 ns tBCLKS BCLK Period 39.0 19.0 ns tSIS SYNC Input Setup Before BCLK Sample Edge 2.25 2.25 ns tSIH SYNC Input Hold After BCLK Sample Edge 2.0 2.5 ns tRISS DRXn Input Setup Before BCLK Sample Edge 2.0 1.5 ns tRIHS DRXn Input Hold After BCLK Sample Edge 1.5 0.5 ns Switching Characteristics tDODS DTXn Output Delay After BCLK Drive Edge 16.5 12.0 ns tDOHS DTXn Output Hold After BCLK Drive Edge 3.0 3.0 ns Figure 17. I2S/TDM Port—Target Timing tDOHS tDODS DRIVE EDGE SAMPLE EDGE SYNC BCLK tSIH tRIHS tBCLKW tSIS tRISS MSB - 1 MSB - 1 MSB MSB TRANSMIT DATA (DTXn) CHANNEL RECEIVE DATA (DRXn) CHANNEL |
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