AD4002 datasheet(21/39 Pages) AD

21 / 39 page

Data Sheet

AD4002/AD4006/AD4010

Rev. A | Page 21 of 39

ANALOG INPUTS

Figure 41 shows an equivalent circuit of the analog input structure,

including the overvoltage clamp of the AD4002/AD4006/AD4010.

CEXT

REXT

VIN

REF

IN+

GND

CLAMP

0V TO 15V

RIN

CIN

CPIN

Figure 41. Equivalent Analog Input Circuit

Input Overvoltage Clamp Circuit

Most ADC analog inputs, IN+ and IN−, have no overvoltage

protection circuitry apart from ESD protection diodes. During

an overvoltage event, an ESD protection diode from an analog

input pin (IN+ or IN−) to REF forward biases and shorts the

input pin to REF, potentially overloading the reference or

damaging the device. The AD4002/AD4006/AD4010 internal

overvoltage clamp circuit with a larger external resistor (REXT =

200 Ω) eliminates the need for external protection diodes and

protects the ADC inputs against dc overvoltages.

In applications where the amplifier rails are greater than VREF

and less than ground, it is possible for the output to exceed

the input voltage range (specified in Table 1) of the device. In

this case, the AD4002/AD4006/AD4010 internal voltage clamp

circuit ensures that the voltage on the input pin does not exceed

VREF + 0.4 V and prevents damage to the device by clamping the

input voltage in a safe operating range and avoiding disturbance of

the reference, which is particularly important for systems that

share the reference among multiple ADCs.

If the analog input exceeds the reference voltage by 0.4 V, the

internal clamp circuit turns on and the current flows through

the clamp into ground, preventing the input from rising further

and potentially causing damage to the device. The clamp turns

on before D1 (see Figure 41) and can sink up to 50 mA of current.

When the clamp is active, it sets the overvoltage (OV) clamp flag

bit in the configuration register that is accessed with a 16-bit SPI

read command or via the OV in the status bits. The OV clamp flag

gives an indication of the overvoltage condition when it is set to 0.

The OV clamp flag is a read only sticky bit and is cleared only if the

The c

lamp circuit does not dissipate static power in the off state.

Note that the clamp cannot sustain the overvoltage condition

for an indefinite amount of time.

The external RC filter, formed by the REXT resistor and the CEXT

capacitor (see Figure 41), is usually present at the ADC input

to band limit the input signal. During an overvoltage event,

excessive voltage is dropped across REXT, and REXT becomes part

of a protection circuit. The REXT value can vary from 200 Ω to

20 kΩ for 15 V protection. The CEXT value can be as low as 100 pF

for correct operation of the clamp. See Table 1 for input overvoltage

clamp specifications.

The analog input structure allows the sampling of the true

differential signal between IN+ and IN−. By using these

differential inputs, signals common to both inputs are rejected.

By using IN− to sense a remote signal ground, ground potential

differences between the sensor and the local ADC ground are

eliminated.

Switched Capacitor Input

During the acquisition phase, the impedance of the analog

inputs (IN+ or IN−) can be modeled as a parallel combination

of Capacitor CPIN and the network formed by the series connection

of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically

400 Ω and is a lumped component composed of serial resistors

and the on resistance of the switches. CIN is typically 40 pF and

is mainly the ADC sampling capacitor.

During the conversion phase, in which the switches are open, the

input impedance is limited to CPIN. RIN and CIN make a single-pole,

low-pass filter that reduces undesirable aliasing effects and

limits noise.

RC Filter Values

The RC filter value (represented by R and C in Figure 39 and

Figure 40) and driving amplifier can be selected depending on

the input signal bandwidth of interest at the full throughput.

Lower input signal bandwidth means that the RC cutoff can be

lower, thereby reducing noise into the converter. For optimum

performance at various throughputs, use the recommended

RC values (200 Ω, 180 pF) and the ADA4807-1.

The RC values shown in Table 10 are chosen for ease of drive

considerations and greater ADC input protection. The combi-

nation of a large R value (200 Ω) and small C value results in a

reduced dynamic load for the amplifier to drive. The smaller value

of C means fewer stability and phase margin concerns with the

amplifier. The large value of R limits the current into the ADC

input when the amplifier output exceeds the ADC input range.

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