ADSP-CM409F datasheet(64/124 Pages) AD

64 / 124 page

Rev. A

Page 64 of 124

November 2015

ADSP-CM402F/CM403F/CM407F/CM408F/CM409F

SPECIFICATIONS

For information about product specifications, contact your Analog Devices representative.

OPERATING CONDITIONS

Clock Related Operating Conditions

Table 27 describes the core clock, system clock, and peripheral clock timing requirements. The data presented in the tables applies to all

speed grades found in the Ordering Guide on Page 124 except where expressly noted. Figure 10 provides a graphical representation of the

various clocks and their available multiplier or divider values.

Parameter

Test Conditions/Comments

Min

Nominal

Max

Unit

VDD_INT

Digital Internal Supply Voltage fCCLK ≤ 240 MHz

1.14

1.2

1.26

VDD_EXT

1 Must remain powered (even if the associated function is not used).

Digital External Supply Voltage

3.13

3.3

3.47

VDD_ANA

Analog Supply Voltage

3.13

3.3

3.47

VIH

2 Parameter value applies to all input and bidirectional signals except TWI signals and USB0 signals.

High Level Input Voltage

VDD_EXT = 3.47 V

2.0

VIH_CLKIN

3 Parameter applies to SYS_CLKIN signal.

High Level Input Voltage

VDD_EXT = 3.47 V

2.2

VIHTWI

4, 5

4 Parameter applies to TWI_SDA and TWI_SCL.

5 TWI signals are pulled up to V

BUSTWI. See Table 26.

High Level Input Voltage

VDD_EXT = 3.47 V

0.7 × VVBUSTWI

VVBUSTWI

VIL

Low Level Input Voltage

VDD_EXT = 3.13 V

0.8

VILTWI

4, 5

Low Level Input Voltage

VDD_EXT = 3.13 V

0.3 × VVBUSTWI

Junction Temperature

TAMBIENT = –40°C to +105°C

–40

+125

°C

Table 26. TWI_VSEL Selections and VDD_EXT/VBUSTWI

TWI_DT Setting

VDD_EXT Nominal

VBUSTWI Min

VBUSTWI Nom

VBUSTWI Max

Unit

TWI000

1 Designs must comply with the VDD_EXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.

3.30

3.13

3.30

3.47

TWI100

3.30

4.75

5.00

5.25

Figure 10. Clock Relationships and Divider Values

SYS_CLKIN

USBCLK

SCLK

CCLK

CSEL

÷(1-31)

SSEL

÷(1-31)

DSEL

÷(1-31)

OCLK

OSEL

÷(1-127)

PLLCLK

MSEL

×(1-127)

÷1 or ÷2

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