Data Sheet

ADF4002

Rev. D | Page 3 of 20

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω,

TA = TMAX to TMIN, unless otherwise noted.

Table 1.

B Version1

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

RF CHARACTERISTICS

See Figure 11 for input circuit

RF Input Sensitivity

−10

0

dBm

RF Input Frequency (RFIN)

5

400

MHz

For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/µs

REFIN CHARACTERISTICS

REFIN Input Frequency

20

300

MHz

For REFIN < 20 MHz, ensure SR > 50 V/µs

REFIN Input Sensitivity2

0.8

VDD

V p-p

Biased at AVDD/23

REFIN Input Capacitance

10

pF

REFIN Input Current

±100

µA

PHASE DETECTOR

Phase Detector Frequency4

104

MHz

ABP = 0, 0 (2.9 ns antibacklash pulse width)

CHARGE PUMP

Programmable, see Figure 18

ICP Sink/Source

High Value

5

mA

With RSET = 5.1 kΩ

Low Value

625

µA

Absolute Accuracy

2.5

%

With RSET = 5.1 kΩ

RSET Range

3.0

11

kΩ

See Figure 18

ICP Three-State Leakage

1

nA

TA = 25°C

ICP vs. VCP

1.5

%

0.5 V ≤ VCP ≤ VP − 0.5 V

Sink and Source Current Matching

2

%

0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. Temperature

2

%

VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage

1.4

V

VIL, Input Low Voltage

0.6

V

IINH, IINL, Input Current

±1

µA

CIN, Input Capacitance

10

pF

LOGIC OUTPUTS

VOH, Output High Voltage

1.4

V

Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V

VOH, Output High Voltage

VDD − 0.4

V

CMOS output chosen

IOH

100

µA

VOL, Output Low Voltage

0.4

V

IOL = 500 µA

POWER SUPPLIES

AVDD

2.7

3.3

V

DVDD

AVDD

VP

AVDD

5.5

V

AVDD ≤ VP ≤ 5.5 V

IDD5 (AIDD + DIDD)

5.0

6.0

mA

IP

0.4

mA

TA = 25°C

Power-Down Mode

1

µA

AIDD + DIDD