ADuCM310

Data Sheet

Rev. A Page 4 of 27

SPECIFICATIONS

AVDD = IOVDD = DVDD = 2.9 V to 3.6 V (the input supply voltages). The difference between AVDD, IOVDD, and DVDD must be ≤0.3 V.

AVNEG (the supply voltage) = −5.5 V to −4.65 V. VDACVDD (the VDAC supply voltage) = 3.07 V to 5.35 V (for VDAC6 and VDAC7),

and VDACVDD must be ≥ AVDD. PVDD (the IDAC supply voltage) for the IDACs = 1.8 V to 2.7 V. AVDD ≥ PVDD + 0.4V. VREF= 2.5 V

internal reference, fCORE = 80 MHz, TA = −10°C to +85°C, unless otherwise noted.

For power sequencing, apply power to the AVNEG or VDACVDD pin before connecting the ground pins.

For register and bit information, see the ADuCM310 reference manual, How to Set Up and Use the ADuCM310.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS

All measurements in single-ended

mode, unless otherwise stated

ADC Power-Up Time

5

µs

f

SAMPLE ≥500 kSPS

DC Accuracy

Resolution

14

Bits

Integral Nonlinearity

Input Buffer

Disabled

±1.5

LSB

2.5 V internal reference

Enabled

±2.5

LSB

Disabled

±1.5

LSB

External reference

Differential Nonlinearity

−0.99

±0.7

+1.5

LSB

2.5 V internal reference;

no missing codes

−0.99

±0.7

+1.51

LSB

2.5 V external reference;

no missing codes

DC Code Distribution

±3

LSB

ADC input voltage = 1.25 V dc

ENDPOINT ERRORS

Offset Error (All Channels Except

the Internal Channels)

ADC update rate up to 800 kSPS

Buffer On or Buffer Off

−0.6

±0.2

+0.6

mV

Buffer on, chop mode on and

automatic zero or buffer off

Offset Error Drift1

Buffer On or Buffer Off

±2.5

µV/°C

Buffer on, chop mode on and

automatic zero or buffer off

Full-Scale Error

ADC update rate up to 800 kSPS

Buffer On or Buffer Off

−0.7

±0.2

+0.6

mV

Excluding internal channels

Internal Channels

±0.2

+0.6

% of full scale

Input buffer on; AV

DD/2, IOVDD/2,

PV

DD voltage on PVDD_IDAC2 pin

0.75

1.5

% of full scale

Input buffer on; IDAC0 to IDAC5;

measured with 1.5 V on the IDAC0

to IDAC5 pins

Gain Error Drift1

2

µV/°C

Full-scale error drift minus offset

error drift; all modes; internal

reference

DYNAMIC PERFORMANCE1

f

IN = 665.283 Hz sine wave; fSAMPLE =

100 kSPS; internally unbuffered

channels; the filter on the analog

inputs is a 15 Ω resistor and a 2 nF

capacitor

Signal-to-Noise Ratio (SNR)

Input Buffer

Disabled

80

dB

Includes distortion and noise

components

Enabled

78

dB

Chop mode on

74

dB

Automatic zero