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NRF52805-CAAA-R 데이터시트(PDF) 3 Page - Nordic Semiconductor

부품명 NRF52805-CAAA-R
상세설명  LAUNCH PACK
PDF  4 Pages
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제조업체  NORDIC [Nordic Semiconductor]
홈페이지  https://www.nordicsemi.com/
Logo NORDIC - Nordic Semiconductor

NRF52805-CAAA-R 데이터시트(HTML) 3 Page - Nordic Semiconductor

  NRF52805-CAAA-R Datasheet HTML 1Page - Nordic Semiconductor NRF52805-CAAA-R Datasheet HTML 2Page - Nordic Semiconductor NRF52805-CAAA-R Datasheet HTML 3Page - Nordic Semiconductor NRF52805-CAAA-R Datasheet HTML 4Page - Nordic Semiconductor  
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2020.05.06
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GPIOs available, requiring only 10 external passive components (inc. two crystal load
capacitors). nRF52805 offers the rare combination of low cost and small size, normally
being a trade-off.
The nRF52805 is supported by two Bluetooth Low Energy protocol stacks, SoftDevice
S112 and S113. The S112 and S113 are memory-optimized Peripheral-only stacks supporting
up to 4 connections as a Peripheral concurrently with a Broadcaster. They are Bluetooth
5.1 qualified and supports the following Bluetooth features: high-throughput 2 Mbps and
channel selection algorithm 2 (CSA #2).
The nRF52 DK is the recommended development kit, it emulates the nRF52805, and can
be used as a starting point for development before moving over to a custom board. A
guide on how to use nRF52805 with nRF5 SDK is available.
The nRF52805 SoC is in mass production now, in a 2.48x2.46 WLCSP28 package with 10
GPIOs.
KEY FEATURES
• 64 MHz Arm® Cortex-M4
• 192 KB Flash + 24 KB RAM
• Bluetooth Low Energy
o Bluetooth 5.2
o High-throughput 2 Mbps
o Channel selection algorithm #2
• 2.4 GHz proprietary protocol support
• Ultra-low-power 2.4 GHz multiprotocol radio
o +4 dBm TX power
o -97 dBm RX sensitivity
o 7 mA in TX (4 dBm)
o 4.6 mA in TX (0 dBm)
o 4.6 mA in RX (1 Mbps)
o Integrated balun with single-ended output
• SPI, TWI UART
• 2-channel 12-bit ADC
• Integrated DC/DC regulator
• 0.3
µA in System OFF
• 1.1
µA in System ON with 24 KB RAM retained and RTC running
• Optimized for small two-layer PCB designs
o 2.48x2.46 mm WLCSP package
o Significantly lower cost than four-layer PCB designs
o Only 10 external passive components (inc. two crystal load capacitors)
o 9.5x8.8 mm reference layout is available, giving access to all GPIOs



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