NRF52810-QFAA-R datasheet(202/483 Pages) NORDIC

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Peripherals

DIN

CLK

Band-pass and

Decimation (right)

Band-pass and

Decimation (left)

Master clock

generator

PDM to PCM

Figure 41: PDM module

6.10.1 Master clock generator

The FREQ field in the master clock's PDMCLKCTRL register allows adjusting the PDM clock's frequency.

The master clock generator does not add any jitter to the HFCLK source chosen. It is recommended (but

not mandatory) to use the Xtal as HFCLK source.

6.10.2 Module operation

By default, bits from the left PDM microphone are sampled on PDM_CLK falling edge, bits for the right are

sampled on the rising edge of PDM_CLK, resulting in two bitstreams. Each bitstream is fed into a digital

filter which converts the PDM stream into 16-bit PCM samples, and filters and down-samples them to

reach the appropriate sample rate.

The EDGE field in the MODE register allows swapping Left and Right, so that Left will be sampled on rising

edge, and Right on falling.

The PDM module uses EasyDMA to store the samples coming out from the filters into one buffer in RAM.

Depending on the mode chosen in the OPERATION field in the MODE register, memory either contains

alternating left and right 16-bit samples (Stereo), or only left 16-bit samples (Mono).

To ensure continuous PDM sampling, it is up to the application to update the EasyDMA destination

address pointer as the previous buffer is filled.

The continuous transfer can be started or stopped by sending the START and STOP tasks. STOP becomes

effective after the current frame has finished transferring, which will generate the STOPPED event. The

STOPPED event indicates that all activity in the module are finished, and that the data is available in RAM

(EasyDMA has finished transferring as well). Attempting to restart before receiving the STOPPED event

may result in unpredictable behaviour.

6.10.3 Decimation filter

In order to convert the incoming data stream into PCM audio samples, a decimation filter is included in

the PDM interface module.

The input of the filter is the two-channel PDM serial stream (with left channel on clock high, right channel

on clock low), its output is 2 × 16-bit PCM samples at a sample rate 64 times lower than the PDM clock

rate.

The filter stage of each channel is followed by a digital volume control, to attenuate or amplify the output

samples in a range of -20 dB to +20 dB around the default (reset) setting, defined by GPDM,default. The gain

is controlled by the GAINL and GAINR registers.

As an example, if the goal is to achieve 2500 RMS output samples (16 bit) with a 1 kHz 90 dBA signal

into a -26 dBFS sensitivity PDM microphone, the user will have to sum the PDM module's default gain

4430_161 v1.0

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