DSP56301 datasheet(13/124 Pages) FREESCALE

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Interrupt and Mode Control

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-9

1.6 Interrupt and Mode Control

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After

RESET

is deasserted, these inputs are hardware interrupt request lines.

Table 1-9.

Interrupt and Mode Control

Signal Name

Type

State During

Reset

Signal Description

MODA

IRQA

Input

Mode Select A

Selects the initial chip operating mode during hardware reset and becomes a

level-sensitive or negative-edge-triggered, maskable interrupt request input

IRQA during normal instruction processing. MODA, MODB, MODC, and

MODD select one of sixteen initial chip operating modes, latched into the OMR

when the RESET signal is deasserted.

External Interrupt Request A

Internally synchronized to CLKOUT. If IRQA is asserted synchronous to

CLKOUT, multiple processors can be re-synchronized using the WAIT

instruction and asserting IRQA to exit the Wait state. If the processor is in the

Stop stand-by state and IRQA is asserted, the processor exits the Stop state.

These inputs are 5 V tolerant.

MODB

IRQB

Input

Mode Select B

Selects the initial chip operating mode during hardware reset and becomes a

level-sensitive or negative-edge-triggered, maskable interrupt request input

IRQB during normal instruction processing. MODA, MODB, MODC, and

MODD select one of sixteen initial chip operating modes, latched into the OMR

when the RESET signal is deasserted.

External Interrupt Request B

Internally synchronized to CLKOUT. If IRQB is asserted synchronous to

CLKOUT, multiple processors can be re-synchronized using the WAIT

instruction and asserting IRQB to exit the Wait state. If the processor is in the

Stop stand-by state and IRQC is asserted, the processor will exit the Stop

state.

These inputs are 5 V tolerant.

MODC

IRQC

Input

Mode Select C

Selects the initial chip operating mode during hardware reset and becomes a

level-sensitive or negative-edge-triggered, maskable interrupt request input

IRQC during normal instruction processing. MODA, MODB, MODC, and

MODD select one of sixteen initial chip operating modes, latched into the OMR

when the RESET signal is deasserted.

External Interrupt Request C

Internally synchronized to CLKOUT. If IRQC is asserted synchronous to

CLKOUT, multiple processors can be re-synchronized using the WAIT

instruction and asserting IRQC to exit the Wait state. If the processor is in the

Stop stand-by state and IRQC is asserted, the processor exits the Stop state.

These inputs are 5 V tolerant.

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