LTC3621 datasheet(16/20 Pages) AD

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LTC3621/LTC3621-2

Rev. D

For more information www.analog.com

VOUT

COUT

3621 F02

VIN

CIN

GND

Board Layout Considerations

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3621 (refer to Figure 2). Check the following in

your layout:

5. Keep sensitive components away from the SW pin. The

feedbackresistorsandINTVCCbypasscapacitorsshould

be routed away from the SW trace and the inductor.

6. A ground plane is preferred.

7. Flood all unused areas on all layers with copper, which

reduces the temperature rise of power components.

These copper areas should be connected to GND.

Design Example

As a design example, consider using the LTC3621 in an

application with the following specifications:

VIN = 10.8V to 13.2V

VOUT = 3.3V

IOUT(MAX) = 1A

IOUT(MIN) = 0A

fSW = 2.25MHz

Because efficiency and quiescent current is important at

both 500mA and 0A current states, Burst Mode operation

will be utilized.

Given the internal oscillator of 2.25MHz, we can calcu-

late the inductor value for about 40% ripple current at

maximum VIN:

L =

3.3V

2.25MHz •0.4A







 1–

3.3V

13.2V







 =2.75µH

Giventhis,a2.7µHor3.3µH,>1.2Ainductorwouldsuffice.

COUT will be selected based on the ESR that is required to

satisfy the output voltage ripple requirement and the bulk

capacitance needed for loop stability. For this design, a

22µF ceramic capacitor will be used.

CIN should be sized for a maximum current rating of:

IRMS =1A

3.3V

13.2V









13.2V

3.3V

–1









1/2

= 0.43A

Decoupling the VIN pin with 10µF ceramic capacitors is

adequate for most applications.

APPLICATIONS INFORMATION

1. Do the capacitors CIN connect to the VIN pin and GND

pin as close as possible? These capacitors provide the

AC current to the internal power MOSFETs and their

drivers.

2. Are COUT and L closely connected? The (–) plate of

COUT returns current to GND.

3. The resistive divider, R1 and R2, must be connected

between the (+) plate of COUT and a ground line ter-

minated near GND. The feedback signal VFB should be

routed away from noisy components and traces, such

as the SW line, and its trace should be minimized. Keep

R1 and R2 close to the IC.

4. Solder the exposed pad (Pin 7 for DFN, Pin 9 for MSOP)

on the bottom of the package to the GND plane. Connect

this GND plane to other layers with thermal vias to help

dissipate heat from the LTC3621.

Figure 2. Sample PCB Layout

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