ST10F168 datasheet(69/74 Pages) STMICROELECTRONICS

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ST10F168

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20.5.12 - CLKOUT and READY

VDD = 5V ±10%, VSS = 0V, for Q6 version : TA = -40, +85°C and for Q3 version TA = -40, +125°C, CL = 100pF,

unless otherwise specified

Notes: 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time

for deactivating READY.

The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.

Table 26 : CLKOUT and READY characteristics

Symbol

Parameter

Max. CPU Clock

25MHz

Variable CPU Clock

1/2 TCL = 1 to 25MHz

Unit

Minimum

Maximum

Minimum

Maximum

t29 CC CLKOUT cycle time

2TCL

t30 CC CLKOUT high time

–

TCL – 6

–

t31 CC CLKOUT low time

–

TCL – 10

–

t32 CC CLKOUT rise time

–

t33 CC CLKOUT fall time

–

t34 CC CLKOUT rising edge to ALE falling

edge

-3 + tA

+7 + tA

-3 + tA

7 + tA

t35 SR Synchronous READY setup time to

CLKOUT

–

t36 SR Synchronous READY hold time after

CLKOUT

4–

–

t37 SR Asynchronous READY low time

–

2TCL + 14

–

t58 SR Asynchronous READY setup time

–

t59 SR Asynchronous READY hold time

4–

–

t60 SR Async. READY hold time after RD, WR

high (Demultiplexed Bus) 2

0 + 2tA

+ tC + tF

TCL - 20

+ 2tA + tC + tF

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