ST10F168-Q3 datasheet(64/74 Pages) STMICROELECTRONICS

64 / 74 page

ST10F168

64/74

Notes: 1. RW-delay and tA refer to the following bus cycle.

2. Partially tested, guaranteed by design characterization.

3. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address

changes before the end of RD have no impact on read cycles.

t39 SR Latched CS low to Valid Data In

–

40 + tC + 2tA

–

3TCL - 20

+ tC + 2tA

t41 CC Latched CS hold after RD, WR

6 + tF

–

TCL - 14 + tF

–ns

t82 CC Address setup to RdCS, WrCS

(with RW-delay)

26 + 2tA

–

2TCL - 14 + 2tA

–ns

t83 CC Address setup to RdCS, WrCS

(no RW-delay)

6 + 2tA

–

TCL -14 + 2tA

–ns

t46 SR RdCS to Valid Data In (with

RW-delay)

–

16 + tC

–

2TCL - 24 + tC

t47 SR RdCS to Valid Data In (no

RW-delay)

–

36 + tC

–

3TCL - 24 + tC

t48 CC RdCS, WrCS Low Time (with

RW-delay)

30 + tC

–

2TCL - 10 + tC

–ns

t49 CC RdCS, WrCS Low Time (no

RW-delay)

50 + tC

–

3TCL - 10 + tC

–ns

t50 CC Data valid to WrCS

26 + tC

–

2TCL - 14 + tC

–ns

t51 SR Data hold after RdCS

–0–

t53 SR Data float after RdCS (with

RW-delay) 2

–

20 + tF

–

2TCL - 20 + tF

t68 SR Data float after RdCS (no

RW-delay) 2

–0 + tF

–

TCL - 20 + tF

t55 CC Address hold after RdCS, WrCS

-10 + tF

–

-10 + tF

–ns

t57 CC Data hold after WrCS

6 + tF

–

TCL - 14 + tF

–ns

Table 25 : Demultiplexed bus characteristics (continued)

Symbol

Parameter

Maximum

CPU Clock = 25MHz

Variable CPU Clock

1/2 TCL = 1 to 25MHz

Unit

Minimum

Maximum

Minimum

Maximum

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