6/15

ST16-19RFRDCS

FSD_CHIPSET_B/0104VP2

1.5 STATUS REGISTER

There is only one status register (for reception). This register can be read at the end of each reception. Its

contents is modified by the end of frame interruption. It provides the status of the last received frame.

In order to access this register, after the last byte received in reception, take the Mic_Ctrl_Data line high

and then read the data.

Rx_Speed_Value: Reception Rate ("00"=106K, "01"=212K, "10"=424K, "11"=424K). Comment: If the

configuration bit Rx_Speed_Config is setting the speed, these bits are the same as configuration bits.

Rx_CRC_OK: CRC Status of the frame (’1’= Wrong, ’0’= OK).

Rx_EGT_TooLong: Bit used to indicate EGT overrun during reception.

Rx_Bad_StopBit: Bit used to indicate if a stop bit wasn’t at ’1’ during frame reception.This is may be due

to bad synchronization.

If there is any mistake during the reception, this one will be stopped. In this case, the status register must

be read to know the failure.