ST24C16 datasheet(3/17 Pages) STMICROELECTRONICS

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Mode

RW bit

MODE pin

Bytes

Initial Sequence

Current Address Read

’1’

START, Device Select, RW = ’1’

Random Address Read

’0’

START, Device Select, RW = ’0’, Address,

’1’

reSTART, Device Select, RW = ’1’

Sequential Read

’1’

1 to 2048

As CURRENT or RANDOM Mode

Byte Write

’0’

START, Device Select, RW = ’0’

Multibyte Write

’0’

VIH

START, Device Select, RW = ’0’

Page Write

’0’

VIL

START, Device Select, RW = ’0’

Note: X = VIH or VIL.

Table 4. Operating Modes

Device Code

Memory MSB Addresses

Bit

Device Select

A10

Note: The MSB b7 is sent first.

Table 3. Device Select Code

memory it responds to the 8 bits received by as-

serting an acknowledge bit during the 9th bit time.

When data is read by the bus master, it acknow-

ledges the receipt of the data bytes in the same

way. Data transfers are terminated with a STOP

condition.

Data in the 4 upper blocks of the memory may be

write protected. The protected area is programma-

ble to start on any 16 byte boundary. The block in

which the protection starts is selected by the input

pins PB0, PB1. Protection is enabled by setting a

Protect Flag bit when the PRE input pin is driven

High.

Power On Reset: VCC lock out write protect. In

order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is implemented. Untill the VCC

voltage has reached the POR threshold value, the

internal reset is active: all operations are disabled

and the device will not respond to any command.

In the same way, when VCC drops down from the

operating voltage to below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable VCC

must be applied before applying any logic signal.

3/17

ST24/25C16, ST24/25W16

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