ST24EM1TR datasheet(9/16 Pages) STMICROELECTRONICS

9 / 16 page

could result in data being overwritten. Note that for

any write mode, the generation by the master of the

STOP condition starts the internal memory pro-

gram cycle. All inputs are disabled until the comple-

tion of this cycle and the ST24/25E16 will not

respond to any request.

Minimizing System Delay by Polling On ACK.

During the internal Write cycle, the ST24/25E16

disable itself from the bus in order to copy the data

from the internal latches to the memory cells. The

maximum value of the Write time (tW) is given in the

AC Characteristics table, this timing value may be

reduced by an ACK polling sequence issued by the

master.

The sequence is:

– Initial condition: a Write is in progress (see Fig-

ure 7).

– Step 1: the Master issues a START condition

followed by a Device Select byte. (1st byte of

the new instruction)

– Step 2: if the ST24/25E16 are internally writ-

ing, no ACK will be returned. The Master goes

back to Step1. If the ST24/25E16 have termi-

nated the internal writing, it will issue an ACK.

The ST24/25E16 are ready to receive the sec-

ond part of the instruction (the first byte of this

instruction was already sent during Step1).

WRITE Cycle

in Progress

AI01099B

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

Send

Byte Address

First byte of instruction

with RW = 0 already

decoded by ST24xxx

Figure 7. Write Cycle Polling using ACK

9/16

ST24E16, ST25E16

ST24EM1TR 데이터시트(PDF) 9 Page - STMicroelectronics

ST24EM1TR 데이터시트(HTML) 9 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

데이터시트 다운로드

링크 URL