MDT10F630

This specification is subject to be changed without notice. Please visit our web site for the most updated information.

http://www.mdtic.com.tw

P.2

2008/4

Ver. 1.0

5. Order Information

Device

ROM

(Words)

RAM

(Bytes)

EEPROM

(Bytes)

I/O

Comparators

Timer

(8/16 bit)

Package

Remark

MDT10F630P11

1.0K

64

128

12

1

1/1

14-DIP

Pin 4 is PA3

function

MDT10F630P13

1.0K

64

128

11

1

1/1

14-DIP

Pin 4 is /MCLR

external reset

function

MDT10F630S11

1.0K

64

128

12

1

1/1

14-SOP

Pin 4 is PA3

function

MDT10F630S13

1.0K

64

128

11

1

1/1

14-SOP

Pin 4 is /MCLR

external reset

function

6. Block Diagram

Stack Eight

Levels

Program

Counters

Oscillator

circuit

Flash ROM

1024 ×14

Instruction

Register

Instruction

Decoder

Working Register

ALU

EEPROM

128×8

Special

Register

Control

Circuit

Status Register

Port A

Port C

Data

8bit

8 bits

10 bits

14 bits

D0~D7

PA0~PA2

PA4~PA5

5 bits

RAM

64 ×8

TMR1

16 Bits

PC0~PC5

6 bits

Comparator

TMR0

8 Bits

PA3

Power on Reset

Watchdog Timer

Power Down Reset