ST5080D datasheet(18/32 Pages) STMICROELECTRONICS

18 / 32 page

CONTROL REGISTER CR0

First byte of a READ or a WRITE instruction to

Control Register CR0 is as shown in TABLE 1.

Second byte is as shown in TABLE 2.

Master Clock Frequency Selection

A master clock must be provided to PIAFE for op-

eration of filter and coding/decodingfunctions.

In COMBO I/II mode, MCLK frequency can be

either 512 kHz, 1.536 MHz, 2.048 MHz or 2.56

MHz.

Bit F1 (7) and F0 (6) must be set during initializa-

tion to select the correct internal divider.

In GCI mode, MCLK must be either 1.536MHz or

2.048MHz.

512KHz and 2.56MHz are not allowed.

Default value is 1.536 MHz for both modes.

Any clock different from the default one must be

selected prior a Power-Up instruction for both

modes.

Coding Law Selection

Bits MA (5) and IA (4) permit selection of Mu-255

law or A law coding with or without even bit inver-

sion.

After power on initialization, the Mu-255 law is se-

lected.

Digital Interface timing

Bit DN=0 (3) selects digital interface in delayed

timing mode while DN=1 selects non delayed

data timing.

In GCI mode, bit DN is not significant.

After reset and if COMBO I/II mode is selected,

delayed data timing is selected.

Digital Interface format

Bit FF=0 (2) selects digital interface in Format 1

where B1 and B2 channel are consecutive. FF=1

selects Format 2 where B1 and B2 channel are

separated by two bits. (see digital interface format

section).

In GCI mode, bit FF is not significant.

56+8 selection

Bit ’B7’ (1) selects capability for PIAFE to take

into account only the seven most significant bits

of the PCM data byte selected.

When ’B7’ is set, the LSB bit on DR is ignored and

LSB bit on DX is high impedance. This function al-

lows connection of an external ”in band” data

generator directly connected on the Digital Inter-

face.

Digital loopback

Digital loopback mode is entered by setting DL

bit(0) equal 1.

In Digital Loopback mode, data written into Re-

ceive PCM Data Register from the selected re-

ceived time-slot is read-back from that Register in

the selected transmit time-slot on DX. Time slot is

selected with Register CR1.

No PCM decoding or encoding takes place in this

mode. Transmit and Receive amplifier stages are

muted.

CONTROL REGISTER CR1

First byte of a READ or a WRITE instruction to

Control Register CR1 is as shown in TABLE 1.

Second byte is as shown in TABLE 3.

Hands-free I/Os selection

Bit HFE set to one enables HFI, HFO pins for

connection of an external handfree circuit such as

TEA 7540. HFO is an analog output that provides

the receive voice signal. 0 dBMO level on that

output is 0.491 Vrms (1.4Vpp). HFI is an analog

high impedance input (10 K

Ω typ.) intended to

send back the processed receive signal to the

Loudspeaker. 0 dBMO level on that input is

0.491Vrms.

Anti-larsen selection

Bit ALE set to one enables on-chip antilarsen and

squelch effect system.

Latch output control

Bit DO controls directly logical status of latch out-

put LO: ie, a ”ZERO” written in bit DO puts output

LO in high impedance, a ”ONE” written in bit DO

sets output LO to zero.

Mu 255 law

True A law even bit

inversion

A law without even bit

inversion

msb

lsb

msb

lsb

msb

lsb

Vin = + full scale

00000010

1010

101111111

Vin = 0 V

Vin = - full scale

00000000

1010

100111111

MSB is always the first PCM bit shifted in or out of PIAFE.

ST5080A

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