ST52T400 datasheet(38/94 Pages) STMICROELECTRONICS

38 / 94 page

ST52T400/T440/E440/T441

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4.2 Global Interrupt Request Enabling

When an Interrupt occurs, it generates a Global

Interrupt Pending (GIP), which can be masked by

software. After a GIP, a Global Interrupt Request

(GIR) will be generated and an Interrupt Service

Routine associated to the interrupt with higher pri-

ority will start. In order to avoid possible conflicts

between interrupt masking set in the main pro-

gram, or inside macros, the GIP is masked

through the User Global Interrupt Mask or the

Macro Global Interrupt Mask (see Figure 4.3).

UEGI/UDGI instruction switches the User Global

Interrupt Mask on/off, enabling/disabling the GIR

for the main program.

MEGI/MDGI instructions switches the Macro Glo-

bal Interrupt Mask on/off in order to ensure that

the macro will not be broken.

4.3 Interrupt Sources

ST52x400/440/441

manages

interrupt

signals

generated by the internal peripherals (PWM/

TIMER, TRIAC Driver and Analog Comparator) or

deriving from the External Interrupt on pin PA7.

The External Interrupt can be programmed to be

active on the rising or falling edge of INT/PA7 sig-

nal by setting the PEXTINT bit of the Configura-

tion Register to 0.

WARNING:

Changing the interrupt priority an

interrupt request is generated.

Each peripheral can be programmed in order to

generate the associated interrupt; further details

are described in the related chapter.Configuration

Brown-Out (see the related chapter).

4.4 Interrupt Maskability

The interrupts can be masked by configuring the

Configuration Register 0 by means of an LDCR or

an LDCE instruction. The interrupt is enabled

when the bit associated to the mask interrupt is

“1". Viceversa, when the bit is ”0", the interrupt is

masked and is kept pending.

For example:

LDRC

10,6

(loads the constant 6 in the RAM

LDCR

0,10

(sets REG_CONF0 with the value

stored in RAM Register 10)

the result is REG_CONF0=00000110, enabling

the interrupts coming from the Analog Comparator

(INT_AC) and from the PWM/TIMER (INT_PWM/

TIMER).

Reset Configuration ‘00000000’

Table 4.1 Configuration Register 0

Description

Bit

Name

Value

Description

MSKE

External Interrupt

Masked

External Interrupt

Not Masked

MSKAC(*)

Analog

Comparator

Interrupt

Masked

Analog

Comparator

Interrupt Not

Masked

MSKTM

PWM/TIMER

Interrupt

Masked

PWM/TIMER

Interrupt

Not Masked

MSKTRF

TRIAC Falling

Edge Interrupt

TRIAC Falling

Edge Interrupt

Not Masked

MSKTRR

TRIAC Rising

Edge Interrupt

Masked

TRIAC Rising

Edge Interrupt

Not Masked

MSKTRP

TRIAC Pulse

Interrupt Masked

TRIAC Pulse

Interrupt Not

Masked

PEXTINT

External

Interrupt active

on Rising Edge

External

Interrupt active

on Falling Edge

MSKBR

Brown-Out

Disabled

Brown-Out

Enabled

(*) Not Used in ST52x400 devices

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