ST52T410 datasheet(24/84 Pages) STMICROELECTRONICS

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ST52T410/ST52T420/E430

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3 EPROM

EPROM memory provides an on-chip user-

programmable non-volatile memory, which allows

fast and reliable storage of user data.

EPROM memory can be locked by the user. In

fact, a memory location called Lock Cell is devoted

to lock EPROM and avoid external operations. A

software identification code, called ID CODE,

distinguishes which software version is stored in

the memory.

32 kbits of memory space with an 8-bit internal

parallelism (up to 4 kbytes) addressed by a 12-bit

bus are available. The data bus is 8 bits.

Memory has a double supply: VPP is equal to

12V

±5% in Programming Phase or to V

SS during

Working Phase. VDD is equal to 5V±10%.

ST52T410/ST52x420 EPROM memory is divided

into three main blocks (see Figure ):

Interrupt Vectors memory block (3 through 17)

contains the addresses for the interrupt routines.

Each address is composed of three bytes.

Figure 3.1 Program Memory Organization

Mbfs Setting memory block (18 through

MemAdd) contains the coordinates of the

vertexes of every Mbf defined in the program.

The maximum value of MemAdd is 1023. This

area is dynamically assigned according to the

size of the fuzzy routines. The unused memory

area, if any, is assigned to the Program

Instruction Set memory block.

The Program Instructions Set memory block

(MemAdd through 4095) contains the instruction

set of the user program.

Locations 0, 1 and 2 contain the address of the first

microcode instruction.The operations that can be

performed on EPROM during the Programming

Phase are: Stand By, Memory Writing, Reading

and Verify/Margin Mode, Memory Lock, IDCode

Writing and Verify.

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