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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PSD413A1 데이터시트(PDF) 85 Page - STMicroelectronics |
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PSD413A1 데이터시트(HTML) 85 Page - STMicroelectronics |
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85 / 123 page  PSD4XX Family 82 -70 -90** -15 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max Min Max OFF * Unit I/O Input or Feedback to tPD Combinatorial Output Port B, E 25 30 34 Add 10 ns tRPD Registered Input to (Note 1) 27 32 36 Add 10 ns Combinatorial Output tEA Input to Output Enable Any Input 25 28 32 Add 10 ns tER Input to Output Disable Any Input 25 28 32 Add 10 ns tARP Register Clear or Preset Any Input 27 30 34 Add 10 ns Delay tARPW Register Clear or Preset Any Input 20 25 29 ns Pulse Width tARD Array Delay 16 18 22 ns Combinatorial Delays (5 V ± 10% Versions) NOTE: 1. Port A and latched address from ADIO (A0, A1, A8 – A15). **If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters. **The -90 speed is available only on Industrial Temperature Range product. 13.7 AC/DC Parameters – ZPLD Timing Parameters (5 V ± 10% Versions) -70 -90** -15 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max Min Max OFF * Unit Maximum Frequency External Feedback 1/(tS + tCO) 30.30 27.03 23.81 MHz Maximum Frequency fMAX Internal Feedback (fCNT) 1/(tS+tCO–10) 43.48 37.04 31.25 MHz Maximum Frequency Pipelined Data 1/(tCH + tCL) 50.00 41.67 33.33 MHz t S Input Setup Time Any Input 15 17 20 Add 10 ns t H Input Hold Time Any Input 0 0 0 0 ns t CH Clock High Time Clock Input 10 12 15 0 ns t CL Clock Low Time Clock Input 10 12 15 0 ns t CO Clock to Output Delay Clock Input 18 20 22 0 ns tARD Array Delay for Product Term Expansion Any Macrocell 16 18 22 0 ns tMIN Minimum Clock Period t CH + t CL 20 24 29 0 ns Synchronous Clock Mode (5 V ± 10%) **If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters. **The -90 speed is available only on Industrial Temperature Range product. |
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