ST52F514GMB6 datasheet(67/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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10.3.4

Multiple Channels Continuous Mode.

In this mode (CONT=1, SEQ=1) a continuous

conversion flow is entered by a start event on the

selected channel sequence. The CH2-0 bits

indicate the last channel of the sequence.

At the end of each conversion the relative Input

Registers are updated with the last conversion

results, while the former values are lost.

The conversion continues until a stop command is

executed by writing a ‘0’ in the apposite AD_CR

Configuration Register bit STR.

10.4 Power Down Mode

Before enabling any A/D operation modes, set the

Power On bit (POW) of the Configuration Register

AD_CR to ‘1’ and then start the A/D Converter by

setting the STR bit. It is suggested to execute the

pre-charging after the Power on to speed-up the

auto calibration process. Clearing the Power On bit

is useful when the A/D is not used, reducing the

total chip power consumption. This state is also the

reset configuration and it is forced by hardware

when the core is in HALT state (after a HALT

instruction execution).

10.5 A/D Converter Register Description

The following registers are related to the use of the

A/D Converter.

10.5.1 A/D Converter Configuration Registers.

A/D Converter Control Register 1 (AD_CR1)

Configuration Register 8 (08h) Read/Write

Reset Value: 0000 0000 (00h)

Bit 7-5: CH2-CH0 Channel Number

The number specified identifies the number

of channels to be converted (Multiple

Channel mode) or the channel to be

converted (One Channel mode)

Bit 4: SCK A/D speed mode

0: Slow mode (800 kHz)

1: Fast mode (1600 kHz)

Bit 3: SEQ One/Multiple Channel Mode

0: One Channel Mode

1: Multiple Channel Mode

Bit 2: POW A/D Converter Power Down/Up

0: Power down

1: Power up

Bit 1: CONT Single/Continuous Mode

0: Single Mode

1: Continuous Mode

Bit 0: STR A/D Converter Start bit

0: A/D Converter stopped

1: A/D Converter started

A/D Converter Control Register 2 (AD_CR2)

Configuration Register 47 (02Fh) Read/Write

Reset Value: 0000 0000 (00h)

Bit 7-5: not used

Bit 4: PRECH Pre-charging process on/off

0: Pre-charge on (default)

1: Pre-charge off

Bit 3: REF Voltage Reference (VREF) source

0: Internal from Vdd

1: External from VREF pin

Bit 2: RESOL 8/10 bits resolution

0: 10 bits

1: 8 bits

Bit 1: INT1 Overflow interrupt mask

0: interrupt disabled

1: interrupt enabled (if MSKAD=1)

Bit 0: INT0 End of Conversion interrupt mask

0: interrupt disabled

1: interrupt enabled (if MSKAD=1)

CH2

CH1

CH0

SCK

SEQ

POW

CONT

STR

PRECH

REF

RESOL

INT1

INT0

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