ST62T32B datasheet(53/86 Pages) STMICROELECTRONICS

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ST62T32B ST62E32B

4.3.5 CONTROL REGISTERS

Status Control Register 1 (SCR1)

Address: E8h - Read/Write/Clear only

Bits 7 & 6 = PSC2..PSC1.

Clock Prescaler. These

bits define the prescaler options for the prescaler

to the Counter Register according to the following

table.

The Prescaler must be disabled (PSC2 = 0, PSC1

= 0) before a new prescaler factor is set if the

counter is running (after a hardware reset the

prescaler is automatically disabled).

To avoid inconsistencies in timing, the prescaler

factor should be set first, and then the counter

started.

Bit 5 = RELOAD. Reload enabled. When set this

bit enables reload from RLCP register into CT reg-

ister. On the contrary, if RELOAD is cleared,

RLCP is used as target for capture from the coun-

ter CT register.

Bit 4 = RUNRES.

Run/Reset. This bit enables the

RUN or RESET operation of the ARTIMER.

If 0, the counter CT is cleared to zero, and is

stopped. Setting this bit to 1 permits the startup of

the counter, and enables the synchronisation cir-

cuits for the timer inputs CP1 and CP2.

Bit 3 = OVFIEN.

Overflow Int. Enable. The Over-

flow Interrupt is masked when this bit is 0.

Setting the bit to 1 enables the overflow flag to set

the ARTIMER interrupt.

Bit 2 = OVFFLG. When this bit is 0, no overflow

has occurred since the last clear of this bit. If the

bit is at 1, an overflow has occurred.

This bit cannot be set by program, only cleared.

Bit 1 = OVFMD. The Overflow Output mode is set

by this bit; when 0, the overflow output is run in set

mode (OVF will be set on the first overflow event,

and will be reset when OVFFLG is cleared). When

1 the overflow output is in toggle mode; OVF tog-

gles its state on every overflow event (independ-

ent to the state of OVFFLG).

Bit 0 = This bit is reserved and must be set to 0.

Status Control Register 2 (SCR2)

Address: E1h - Read/Write/Clear only

Bit 7 = Reserved. Must be kept cleared.

Bit 6 = CP1ERR.

CP1 Error Flag. This bit is set to

1 if a new CP1 event has taken place since

CP1FLG was set to signal an error condition, it is 0

if there has been no event.

It is recommended to clear CP1ERR at any time

that CP1FLG is cleared, as further CP1 events

cannot be recognised if CP1ERR is set. This bit

cannot bet set by write, only cleared.

Bit 5 = CP2ERR.

CP1 Error Flag. This bit is set to

1 if a new CP2 event has taken place since

CP2FLG was set to signal an error condition, it is 0

if there has been no event.

It is recommended to clear CP2ERR at any time

that CP2FLG is cleared, as further CP2 events

cannot be recognised if CP2ERR is set. This bit

cannot bet set by write, only cleared.

Bit 4 = CP1IEN.

CP1 Interrupt Enable.CP1 The

Capture 1 Interrupt is masked when this bit is 0.

Setting the bit to 1 enables the CP1 event flag

CP1FLG to set the ARTIMER interrupt.

Bit 3 = CP1FLG.

CP1 Interrupt Flag. When this bit

is 0, no CP1 event has occurred since the last

clear of this bit. If the bit is at 1, a CP1 event has

occurred.

This bit cannot be set by program, only cleared.

Bit 2 = CP1POL.

CP1 Edge Polarity Select.

CP1POL defines the polarity for triggering the CP1

event.

A 0 defines the action on a falling edge on the CP1

input, a 1 on a rising edge.

Bit 1 & 0 = RLDSEL2..RLDSEL1.

Reload Source

Select. These bits define the source for the reload

events; they do not affect the operation of the cap-

ture modes.

PSC2

PSC1 RELOAD RUNRES OVFIEN OVFFLG OVFMD

PSC2

PSC1

Function

Clock Disabled (prescaler and counter

stopped

Prescale by 1

Prescale by 4

Prescale by 16

CP1ERR CP2ERR CP1IEN CP1FLG CP1POL RLDSEL2 RLDSEL1

RLDSEL2 RLDSEL1

Fun ction

Reload and startup triggered by

RUNRES

Reload triggered by every CP1

event

Reload triggered by every CP2

event

Reload disabled

157

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