ST62T42B datasheet(50/68 Pages) STMICROELECTRONICS

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ST62T42B/E42B

LCD CONTROLLER-DRIVER (Continued)

5.4.4 Stand by or STOP operation mode

No clock from the main oscillator is available in

STOP mode for the LCD controller, and the con-

troller is switched off when the STOP instruction is

executed. All segment and common lines are then

switched to ground to avoid any DC biasing of the

LCD elements.

5.4.5 LCD Mode Control Register (LCDCR)

Address: DCh - Read/Write

Bits 7-6 = DS0, DS1.

Multiplexing ratio select bits.

These bits select the number of common back-

planes used by the LCD control.

Bits 5-3 = HF0, HF1, HF2.

Oscillator select bits.

These bits allow the LCD controller to be supplied

with the correct frequency when different high

main oscillator frequencies are selected as system

clock. Table 18 shows the set-up for different clock

crystals.

Bits 2-0 = LF0, LF1, LF2.

Base frame frequency

select bits. These bits control the LCD base oper-

ational frequency of the LCD common lines.

LF0, LF1, LF2 define the 32KHz division factor as

shown in Table 21.

Table 21. 32KHz Division Factor for Base

Frequency Selection

DS1

DS0

HF2

HF1

HF0

LF2

LF1

LF0

LF2

LF1

LF0

32KHz Division Factor

000

512

001

386

010

256

011

192

100

128

101

110

Reserved

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