ST6262BB3 datasheet(17/68 Pages) STMICROELECTRONICS

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ST62T52B ST62T62B/E62B

CLOCK SYSTEM (Cont’d)

Oscillator Control Registers

Address: DCh

—

Write only

Bit 7-4. These bits are not used.

Bit 3. Reserved. Cleared at Reset. THIS BIT

MUST BE SET TO 1 BY USER PROGRAM to

achieve lowest power consumption.

Bit 2. Reserved. Must be kept low.

RS1-RS0. These bits select the division ratio of

the Oscillator Divider in order to generate the in-

ternal frequency. The following selctions are avail-

able:

Note: Care is required when handling the OSCR

son, it is not allowed to change the OSCR con-

tents while executing interrupt service routine, as

the service routine cannot save and then restore

its previous content. If it is impossible to avoid the

writing of this register in interrupt service routine,

an image of this register must be saved in a RAM

location, and each time the program writes to

OSCR it must write also to the image register. The

image register must be written first, so if an inter-

rupt occurs between the two instructions the

OSCR is not affected.

Figure 9. Clock Circuit Block Diagram

---

OSCR

RS1

RS0

RS1

RS0

Division Ratio

MAIN

OSCILLATOR

Core

: 13

: 12

: 1

Timer

Watchdog

POR

fINT

ADC

AR Timer

OSCILLATOR

DIVIDER

RS0, RS1

OSCin

OSCout

fOSC

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