ST6373J2B1 datasheet(42/64 Pages) STMICROELECTRONICS

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ST6373

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SYNC PROCESSOR (Cont’d)

Period Counter 2 And Blank Control Register

(PCBCR)

Address: F1h - Read/Write

Reset Value: XFh

b7: Not Used

b6: BOS:

Blank Output Selection

0=PA5, 1=BLANK, Write Only, 0 after Reset

b5: VFLYF:

Vertical FLY-back Flag

Set on falling edge of VFLY/PB6 input, Read and

Write, cleared by S/W (write of zero), undefined af-

ter Reset

b4: HFLYF: Horizontal FLY-back Flag

Set on falling edge of HFLY/PB5 Input, Read and

Write, cleared by S/W (write of zero), undefined af-

ter Reset

b3 to b0: 4 MSB bits of period counting result,

Read Only, Fh After Reset

Figure 27. SYNC Processor Block Diagram

BOS

VFLY

HFLY

V11

V10

VSYNCO

CLMPO

HSYNCO

HVGEN

COPC

CMCT

VSYNCO

POLARITY

VSYNCI

HSYNCI

HDRIVE

SHH

Blk

V 12 bit TIMER

(VACQ)

HSYNCO

POLARITY

H 12 bit Event Counter

(timer 3)

VSYNCI

HSYNCI

H Polarity Detector

HPF

HVGEN

HVOS

CMW0:1

VSYNCEN

VOPC

HOPC

BLKEN

PA5/BLK0

To Edge detector (HFLYF)

To Edge detector (VFLYF)

PB5/HFLY

PB6/VFLY

PA3/VSYNCO

HFLY, VFLY, VSYNCO signals should have positive polarity

Blank Out Generation

VR02089A

VSYNC+

Generator

61 Hz,64

µs

HSYNC+

Generator

62.5 kHz, 2

µs

Sync Generator

H/W Block

BACK PORCH

CLAMP

GENERATOR

CLAMP

POLARITY

Latch

Pulse

Detect

Polarity

Detector

VPF

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