ST70235A

14/28

Figure 11 : Generic Processor Interface Read Timing Cycle

Generic processor interface Cycle Timing

All AC characteristics are indicated for a 100pF capacitive load.Cycle timing for generic interface.

The timing are generally presented with the write signal, but as shown on the read diagram, they are also

valid for the read signal, so for example the Trdy2wr timing is the same as what can be Trdy2rd.

Table 2 : Cycle timing

Symbol

Parameters

Minimum

Maximum

Unit

Tcsre

Access Time

900

µs

Talew

Ale pulse width

12

ns

Tavs

Address valid setup time

10

ns

Tavh

Address valid hold time

10

ns

Tale2cs

ALE to CSB

0

ns

Tale2Z

ALE to high Z state of bus

50

ns

Tcs2wr

CSB to WRB

0

ns

Tcs2rd

CSB to RDB

0

ns

Twr2d

WR to data

15

ns

Twr2rdy

WR to Dy asserted

60

ns

Trd2rdy

RD to Rdy asserted

60

ns

Trdy2wr

Rdyb to WRB

0

ns

Trdy2rd

Rdyb to RDB

0

ns

Tdvs

Data valid setup time

10

ns

Tdvh

Data valid hold time

1/2 Tmclk

Tmclk

ns

Trdy2cs

RdyB to CSB

0

ns

Tmclk

master clock timing : cf specifications

Twr2Mclk

Setup time according to the master clock

10

ns

Trd2Mclk

Setup time according to the master clock

10

ns

ALE

CSB

Address/DATA

RDB

RDYB

MClk

1

1: WRB = BE1 is high.