ST72511R datasheet(25/164 Pages) STMICROELECTRONICS

부품명	ST72511R

상세설명	8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES

PDF	164 Pages

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제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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25 / 164 page

ST72311R, ST72511R, ST72512R, ST72532R

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5.2 RESET SEQUENCE MANAGER (RSM)

5.2.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 12:

External RESET source pulse

Internal LVD RESET (Low Voltage Detection)

Internal WATCHDOG RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 11:

Delay depending on the RESET source

4096 CPU clock cycle delay

RESET vector fetch

The 4096 CPU clock cycle delay allows the oscil-

lator to stabilise and ensures that recovery has

taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock

cycles.

Figure 11. RESET Sequence Phases

Figure 12. Reset Block Diagram

RESET

DELAY

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

fCPU

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

ST72511R 데이터시트(PDF) 25 Page - STMicroelectronics