ST72C171 datasheet(36/152 Pages) STMICROELECTRONICS

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ST72C171

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7.2 MISCELLANEOUS REGISTERS

7.2.1 Miscellaneous Register 1 (MISCR1)

Miscellaneous register 1 is used select SLOW op-

erating mode. Bits 3, 4, 6, and 7 determine the po-

larity of external interrupt requests.

—

Read /Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = PEI[3:2]

Polarity Options of External In-

terrupt ei1. (Port B).

These bits are set and cleared by software. These

bits determine which event causes the external in-

terrupt (ei1) on port B according to Table 8.

Table 8. ei1 Ext. Int. Polarity Options

Bit 5 = MCO

Main clock out selection

This bit enables the MCO alternate function on the

I/O port. It is set and cleared by software.

0: MCO alternate function disabled

(I/O pin free for general-purpose I/O)

1: MCO alternate function enabled

(fOSC/2 on I/O port)

This bit is set and cleared by software. When set it

can be used to output the internal clock to the ded-

icated I/O port.

Bit 4:3 = PEI[1:0]

Polarity Options of External In-

terrupt ei0. (Port A)

These bits determine which event causes the ex-

ternal interrupt (ei0) on port A according to Table

Table 9. ei0 Ext. Int. Polarity Options

Bit 2:1 = CP[1:0]

CPU clock prescaler

These bits are set and cleared by software. They

determine the CPU clock when the SMS bit is set

according to the following table.

Table 10. fCPU Value in Slow Mode

Bit 0 = SMS

Slow Mode Select

This bit is set and cleared by software.

0: Normal Mode - fCPU = fOSC/ 2

1: Slow Mode - the fCPU value is determined by the

PC[1:0] bits.

PEI3

PEI2

MCO PEI1 PEI0 CP1

CP0

SMS

MODE

PEI3

PEI2

Falling edge and low level

(Reset state)

Rising edge only

Falling edge only

Rising and falling edge

MODE

PEI1

PEI0

Falling edge and low level

(Reset state)

Rising edge only

Falling edge only

Rising and falling edge

fCPU Value

CP1

CP0

fOSC / 4

fOSC / 8

fOSC / 16

fOSC / 32

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