III.3 - AC Electrical Characteristics

III.3.1 - Dual Port RAM Host Timing

Number

Description

Min.

Typ.

Max.

Unit

1

Address and Control Set-up Time

5

ns

2

SDTACK Acknowledge

20

ns

3

Data Set-up Time

10

ns

4

Address and Control Hold Time

0

ns

5

Data Hold Time

5

ns

6

SDTACK Hold Time

0

ns

7

Write Enable Low State

45

ns

8

Access Inhibition High State (see Note)

70

ns

9

Read Enable Low State

45

ns

10

Read Data Access

35

ns

11

SINTR Clear Delay

50

ns

12

Data Valid to Tristate

15

ns

Note :

A minimum delay of 70ns is required only from the rizing edge of NWRITE to the falling edge of the next selected NREAD or NWRITE.

19

4

NSCS

SA[0..6]

SR/NW

SD[0..7]

WRITE-CYCLE TIMING

Valid Address

READ-CYCLE TIMING

Valid Address

Valid Data

OUT

NSDS

NSDTACK

NSINTR

SR/NW (= NWRITE)

NSDS (= NREAD)

17

4

8

3

5

10

5

12

26

26

11

Valid Data

IN

ST75C520

8/45