ST92R195B datasheet(13/18 Pages) STMICROELECTRONICS

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ST92R195B - ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS

PIN CAPACITANCE

(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))

CURRENT CONSUMPTION

(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified)

Notes:

1. Port 0 is configured in push-pull output mode (output is high). Ports 2, 3, 4 and 5 are configured in bi-directional weak pull-up mode resistor.

The external CLOCK pin (OSCIN) is driven by a square wave external clock at 8 MHz. The internal clock prescaler is in divide-by-1 mode.

2. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to

VSS, HSYNC is driven by a 15625Hz clock.

All peripherals working including Display.

3. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to

VSS, HSYNC is driven by a 15625Hz clock.

The TDSRAM interface and the Slicers are working; the Display controller is not working.

4. VSYN C and HSYNC tied to

VSS. External CLOCK pin (OSCIN) is held low. All peripherals are disabled.

EXTERNAL INTERRUPT TIMING TABLE (rising or falling edge mode)

DD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))

TpC is the INTCLK clock period.

Symbol

Parameter

Conditions

Value

Unit

min

max

CIO

Pin Capacitance Digital Input/Output

Symbol

Parameter

Condition s

Value

Unit

min

typ.

max

IDD1

Run Mode Current

notes 1,2; all On

100

IDDA1

Run Mode Analog Current

(pin VDDA)

Timing Controller On

IDD2

HALT Mode Current

notes 1,4

100

µA

IDDA2

HALT Mode Analog Current

(pin VDDA)

notes 1,4

100

µA

Symbol

Parameter

Condition s

Value

Unit

INTCLK=24 MHz.

min

max

TwLR

Low level pulse width

TpC+12

TwHR

High level pulse width

TpC+12

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