ST92F120JR1T datasheet(317/320 Pages) STMICROELECTRONICS

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ST92F120 - ELECTRICAL CHARACTERISTICS

A/D ANALOG SPECIFICATIONS

(VDD =5V ± 10%, TA = –40°C to +105°C, fINTCLK = 24MHz, unless otherwise specified)

Note:

(1) “1LSBideal” has a value of AVDD/256

(2) Including sample time

(3) This is the internal series resistance before the sampling capacitor

(4) This is a typical expected value, but not a tested production parameter.

If V(i) is the value of the i-th transition level (0

≤ i ≤ 254), the performance of the A/D converter has been evaluated as follows:

OFFS ET ERROR= deviation between the actual V(0) and the ideal V(0) (=1/2 LSB)

GAIN ERROR= deviation between the actual V(254) and the ideal V(254) - V(0) (ideal V(254)=AVDD-3/2 LSB)

DNL ERROR= max {[V(i) - V(i-1)]/LSB - 1}

INL ERROR= max {[V(i) - V(0)]/LSB - i}

ABS. ACCURA CY= overall max conversion error

(5) Simulated value, to be confirmed by characterisation.

(6) The specified values are guaranteed only if an overload condition occurs on a maximum of 2 non-selected analog input pins and the

absolute sum of input overload currents on all analog input pins does not exceed

±10 mA.

Parameter

Typical

Minimum

Maximum

Units (1)

Notes

Conversion time

138

INTCLK

(2)(6)

Sample time

INTCLK

(6)

Power-up time

µs

(6)

Resolution

bits

Monotonicity

GUARANTEED

No missing codes

GUARANTEED

Zero input reading

Hex

(6)

Full scale reading

Hex

(6)

Offset error

0.3

0.5

LSBs

(1)(4)(6)

Gain error

0.6

LSBs

(4)(6)

DLE (Diff. Non Linearity error)

0.6

LSBs

(4)(6)

ILE (Int. Non Linearity error)

1.0

LSBs

(4)(6)

TUE (Absolute Accuracy)

–

1.0

LSBs

(4)(6)

Input Resistance

1.3

0.8

2.7

Ω

(3)(5)(6)

Hold Capacitance

1.4

(5)(6)

Input Leakage

±1

µA

(6)

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