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STA001

Table 2. First data byte selection table (selection of synthesizer channel) using a 14.725Mhz quartz

Table 3. Second data byte selection table (LOCK test on both pll, dividers test and IF pll test)

MSB

LSB

RF LO freq. selected

Units

Division ratio

selected on

synthesizer

Notes

D6

D5

D4

D3

D2

D1

D0

from REF1 to

LO1

0

0

0

0

1

1

0

1325.25 +6*0.46015625

(1328.010938)

MHz

360.75

Lowest

selectable

freq.

0

0

0

0

1

1

1

1325.25 +7*0.46015625

MHz

360.875

0

0

0

1

0

0

0

1325.25+ 8*0.46015625

MHz

361

--

-

-

-

-

-

0

0

1

1

1

0

0

1338.134375

MHz

363.5

first used freq.

-

-

-

-

-

-

-

1325.25+

N*0.46015625

N=(D6..D0) represented

decimal number

MHz

360 + N*0.125

general freq.

generation

rule

1

1

0

1

1

0

1

1375.407031

MHz

373.625

Last used freq.

--

-

-

-

-

-

1

1

1

1

1

1

0

1383.229688

MHz

375.75

1

1

1

1

1

1

1

1383.689844

MHz

375.875

--

-

-

-

-

-

0

0

0

0

1

0

1

1325.25

+133*0.46015625

(1386.450781)

MHz

376.625

Highest

selectable

freq.

1

0

0

0

1

0

1

1357.000781

MHz

368.625

Startup

presetted data

MSB

LSB

Working mode

Notes

D6

D5

D4

D3

D2

D1

D0

00000

00

Lock test on RF pll

lock flag to be tested: TLCK;

Startup presetted data

00001

00

Lock test on IF pll

lock flag to be tested: TLCK

00000

01

Lock test on RF and IF pll

lock flag to be tested: TLCK

00100

10

First pll programmable

divider test

output freq. divided by 16

available on TLCK

00110

10

First pll reference divider

test

output freq. divided by 8

available on TLCK

00101

10

Second pll fixed divider

test

output freq. divided by 2

available on TLCK

00111

10

Second pll reference

divider test

output freq. available on TLCK

10000

00

Test frequency on IF pll

divider by 1034

Division ratio changed to 987

11000

00

Test frequency on IF pll

divider by 1034

Division ratio changed to 1081