STA015 datasheet(33/44 Pages) STMICROELECTRONICS

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ADPCM_FRAME_SIZE

Address: 0xBD (189)

Type: R/W

Software Reset: 0x13

Hardware Reset: 0x00

MSB

LSB

AFS7 AFS6 AFS5 AFS4 AFS3 AFS2 AFS1 AFS1

The ADPCM frame size may be adjusted to

match a trade-off between the bitrate overhead

and the frame length. The frame size (in bytes) is

calculated as follow:

FRAME size = (ADPCM_FRAME_SIZE * 90)

+108

The frame starts with a 5 bytes sync word

(0x5354445649) and, after that, a frame header:

- 13 bytes for DVI algorithm

- 103 bytes for G726 pack algorithms

ADPCM_INT_CFG

Address: 0xBE (190)

Type: R/W

Software Reset: 0x0B

Hardware Reset: 0x00

MSB

LSB

INTL

Using this register the ADPCM interrupt capability

can be properly configured.

INTL0 -

INTL6

Interrupt Length

The interrupt length can be programmed,

using this bits, from 0 up to 128 system

clock cycles

GPIO_CONF

Address: 0xBF (191)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

GOSP

GISP

This register controls how data are strobed on the

GPIO interface.

GISP:

GPIO Strobe Polarity in INPUT mode

0 =

data strobed an falling edge

1 =

data strobed on rising edge

GOSP:

GPIO Strobe Polarity in OUTPUT mode

0 =

non inverted

1 =

inverted

ADC_WLEN

Address: 0xC0 (192)

Type: R/W

Software Reset: 0x0F

Hardware Reset: 0x0F

MSB

LSB

AWL4 AWL3 AWL2 AWL1 AWL0

To select ADC word length AWL4 through AWL0

bits can be used. This 5 bit value must contain

the size of the significant data bits minus one.

ADC_WPOS

Address: 0xC1 (193)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

AWL4 AWL3 AWL2 AWL1 AWL0

These bits specify the position of the sample

word referred to the LRCK slot boundary. Bit

AWP0 thru AWP4 must be programmed with the

number of bits to ignore after the sample word.

STA015-STA015B-STA015T

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