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STA120 데이터시트(PDF) 10 Page - STMicroelectronics

부품명 STA120
상세설명  DIGITAL AUDIO INTERFACE RECEIVER
PDF  15 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STA120 데이터시트(HTML) 10 Page - STMicroelectronics

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STA120
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The validity flag indicates that the validity bit for a previous sample was high since the last clearing of the
error codes. The slipped sample error can only occur when FSYNC and SCK of the audio serial port are
inputs. In this case, if FSYNC is asynchronous to the received data rate, periodically a stereo sample will
be dropped or reread depending on whether the read rate is slower or faster than the received data rate .
When this occurs, the slipped sample error code will appear on the "E" pins.
The CRC error is updated at the beginning of a channel status block, and is only valid when the profes-
sional format of channel status data is received. This error is indicated when the STA120 calculated CRC
value does not match the CRC byte of the channel status block or when a block boundary changes (as in
removing samples while editing).
The parity error occurs when the incoming sub-frame does not have even parity as specified by the stan-
dards. The biphase coding error indicates a biphase coding violation occurred. The no lock error indicates
that the PLL is not locked onto the incoming data stream. Lock is achieved after receiving three frame pre-
ambles then one block preamble, and is lost after not receiving four consecutive frame preambles.
The receive frequency information is encoded on pins F2, F1 and F0, and is decoded as shown in Table
6. The on-chip frequency comparator compares the received clock frequency to an externally supplied
6.144MHz clock which is input on the FCK pin. The "F" pins. The clock on FCK must be valid for two thirds
of a block for the "F" pins to be accurate.
Table 4. Sample Frequency Decoding
Channel Status Reporting
When SEL is high, channel status is displayed on C0, and Ca-Ce for the channel selected by CS12. If
CS12 is low, channel status for sub-frame1 is displayed, and if CS12 is high, channel status for subframe
2 is displayed. the contents of Ca-Ce depend upon the C0 professional/consumer bit. The information re-
port is shown in Table 5.
Table 5. Channel Status Pins
F2
F1
F0
Error
0
0
0
Out of Range
0
0
1
48KHz ±4%
0
1
0
44.1KHz ±4%
0
1
1
32KHz ±4%
1
0
0
48KHz ±400ppm
1
0
1
44.1KHz ±400ppm
1
1
0
44.056KHz ±400ppm
1
1
1
32KHz ±400ppm
Pin
Professional
Consumer
C0
0 (low)
1 (high)
Ca
C1
C1
Cb
EM0
C2
Cc
EM1
C3
Cd
C9
ORIG
Ce
CRCE
IGCAT



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