EMD12164P datasheet(21/45 Pages) EMLSI

21 / 45 page

EMD12164P

512M: 32M x 16 Mobile DDR SDRAM

Rev 0.0

Preliminary

Operations

Bank/Row Activation

The Bank Activation command is issued by holding CASB and WEB high with CSB and RASB low at the rising edge of

the clock(CK). The DDR SDRAM has four independent banks, so two bank select addresses(BA0, BA1) are required.

The Bank Activation command must be applied before any READ or WRITE operation is executed. The delay from the

Bank Activation command to the first READ or WRITE command must meet or exceed the minimum of RAS to CAS

delay time(tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation com-

mand can be applied to the same bank. The minimum time interval between interleaved Bank Activation com-

mands(Bank A to Bank B and vice versa) is the Bank to Bank delay time(tRRD min).

Bank Activation Command Cycle

CKB

Address

Command

Tn+1

Tn+2

Bank B

Row Addr.

Bank A

Row. Addr.

Bank A

Row Address

Bank A

Col. Addr.

Bank A

Activate

NOP

Write

with Auto

Precharge

Bank B

Activate

NOP

Bank A

Activate

Row Cycle Time(tRC)

: Don'tcare

RAS - CAS delay(tRCD)

RAS - RAS delay time(tRRD)

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