EM742SP16 datasheet(6/10 Pages) EMLSI

6 / 10 page

EM742SP16

256Kx16 Multiplexed STRAM

TIMING WAVEFORM OF READ CYCLE (1) ( WE = VIH )

TIMING DIAGRAMS

Device Operaton

The access is performed in two stages. The first stage is address latching. The first stage take place between point A and

B in timing diagram. At this stage, the Chip Select(CS) to the device is asserted. The random access is enabled either

from the point the address becomes stable, the falling edge of the AVD signal or from the falling edge of the last chip

select signal. The second stage is the read or write access. This takes place between points B and C in timing diagram.

In case of a read access, the multiplexed address/data bus (ADQ0 ~ ADQ15) changes its direction. It is important to notice

tOE when it is dominant that the device gets into the read cycle since the address is available long before the device

output is enabled.

Read Access

The read access is initiated by applying the address to the multiplexed address/data bus or to the address bus over A15

(A16 -> Axx). When the address is stable, the device chip select(CS) is set active low. At point A, the AVD signal is taken

low and the latch becomes transparent. This allows the address to be propagated to the memory array. The address is

stable at the rising edge of the AVD signal. The AVD signal goes high at point B in which the address latch is completed.

At this point the read cycle is entered. The OE signal is set active low. This changes the direction of the bus. The status

of control signals UB and LB are set according to the access. Data is read at point C.

tAVD

tACC1

tAVDS

tAVDH

Address Valid

Data Valid

tOHZ

tHZ

tBHZ

tACC2

tOE

tOLZ

tCSS

tACC3

tUBLBA

tBLZ

AVD

UB, LB

Address/Data

tADOE

EM742SP16 데이터시트(PDF) 6 Page - Emerging Memory & Logic Solutions Inc