−120

−110

−100

−90

−80

−70

−60

−50

−40

f − Frequency − Hz

G010

20

100

1k

10k

20k

Left to Right

Right to Left

PVDD = 18 V

DETAILED DESCRIPTION

POWER SUPPLY

TAS5701

TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

CROSSTALK

vs

FREQUENCY

Figure 17.

The digital portion of the chip requires 3.3 V, and the analog portion can work with a variable range up to 12 V.

PVDD has a maximum operational range up to 22 V.

To facilitate system design, the TAS5701 needs only a 12-V supply in addition to the (typical) 18-V power-stage

supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog

circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is

accommodated by built-in bootstrap circuitry requiring only a few external capacitors.

In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive

and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has

separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Special

attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In

general, inductance between the power supply pins and decoupling capacitors must be avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is

charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the

bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output

potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM

switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors,

size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even

during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the

remaining part of the PWM cycle. In an application running at a reduced switching frequency, generally 192 kHz,

the bootstrap capacitor might need to be increased in value.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB

placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For

optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is

decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin.

16

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