ADE5166 datasheet(42/148 Pages) AD

42 / 148 page

ADE5166/ADE5169/ADE5566/ADE5569

Preliminary Technical Data

Rev. PrB | Page 42 of 148

Table 45. Interrupt Enable 3 SFR (MIRQENH, 0xDB)

Bit

Interrupt Enable Bit

Description

7 to 6

Reserved

Reserved.

WFSM

When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core.

PKI

When this bit is set, the PKI flag set creates a pending ADE interrupt to the 8052 core.

PKV

When this bit is set, the PKV flag set creates a pending ADE interrupt to the 8052 core.

CYCEND

When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.

ZXTO

When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.

When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core.

ANALOG INPUTS

Each ADE5166/ADE5169/ADE5566/ADE5569 has two fully

differential voltage input channels. The maximum differential

input voltage for input pairs VP/VN and IP/IN is ±0.4 V for the

ADE5566 and ADE5569.

For the ADE5166 and ADE5169, PGA1 = 1 is not recommended

because at full scale, when both IPA and IPB are 180° out of phase,

the ADC can be overranged. It is recommended, for these

products, that PGA1 = 2, 4, 8, or 16 be used.

Each analog input channel has a programmable gain amplifier

(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The

gain selections are made by writing to the GAIN register (see

Table 37 and Figure 20). Bit 0 to Bit 2 select the gain for the PGA

in the current channel, and Bit 5 to Bit 7 select the gain for the

PGA in the voltage channel. For the ADE5166 and ADE5169, it

is recommended that PGA1 = 2, 4, 8, or 16 be used. Figure 19

shows how a gain selection for the current channel is made

using the gain register.

K × VIN

000

0000

7654

3210

GAIN[7:0]

GAIN (K)

SELECTION

VIN

Figure 19. PGA in Current Channel

000

654

GAIN REGISTER*

CURRENT AND VOLTAGE CHANNELS PGA CONTROL

PGA2 GAIN SELECT

000 = ×1

001 = ×2

010 = ×4

011 = ×8

100 = ×16

PGA1 GAIN SELECT

000 = ×1

001 = ×2

010 = ×4

011 = ×8

100 = ×16

RESERVED

*REGISTER CONTENTS SHOW POWER-ON DEFAULTS.

ADDR:

0x1B

CFSIGN_OPT

Figure 20. Analog Gain Register

ADE5166 데이터시트(PDF) 42 Page - Analog Devices

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