AT89C51RC2-3CSIM datasheet(90/127 Pages) ATMEL

90 / 127 page

AT89C51RB2/RC2

4180C–8051–12/03

Table 69. Program Lock Bits of the SSB

Note:

U: unprogrammed or "one" level.

P: programmed or "zero" level.

X: don’t care

WARNING: Security level 2 and 3 should only be programmed after Flash and code

verification.

Flash Memory Status

AT89C51RB2/RC2 parts are delivered in standard with the ISP boot in the Flash mem-

ory. After ISP or parallel programming, the possible contents of the Flash memory are

summarized on Figure 35.

Figure 35. Flash Memory Possible Contents

Memory Organization

In the AT89C51RB2/RC2, the lowest 16K or 32K of the 64 KB program memory address

space is filled by internal Flash.

When the EA pin is high, the processor fetches instructions from internal program Flash.

Bus expansion for accessing program memory from 16K or 32K upward automatic since

external instruction fetches occur automatically when the program counter exceeds

3FFFh (16K) or 7FFFh (32K). If the EA pin is tied low, all program memory fetches are

from external memory.

Program Lock Bits

Protection Description

Security

level

LB0

LB1

No program lock features enabled.

ISP programming of the Flash is disabled.

Same as 2, also verify through ISP programming interface is disabled.

0000h

Virgin

3FFFh

Default

After ISP

After Parallel

Programming

After Parallel

Programming

Application

Virgin

After ISP

Dedicated

ISP

Dedicated

ISP

7FFFh T89C51RC2 32KB

T89C51RB2 16KB

Application

Virgin

Application

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