AT89S53_00 datasheet(16/33 Pages) ATMEL

16 / 33 page

AT89S53

Figure 9. SPI Transfer Format with CPHA = 1

*Not defined but normally LSB of previously transmitted character

Interrupts

The AT89S53 has a total of six interrupt vectors: two exter-

nal interrupts (INT0 and INT1), three timer interrupts

(Timers 0, 1, and 2), and the serial port interrupt. These

interrupts are all shown in Figure 10.

Each of these interrupt sources can be individually enabled

or disabled by setting or clearing a bit in Special Function

disables all interrupts at once.

Note that Table 10 shows that bit position IE.6 is unimple-

mented. In the A T89 C5 1, bit positi on IE.5 is als o

unimplemented. User software should not write 1s to these

bit positions, since they may be used in future AT89

products.

Figure 10. Interrupt Sources

MSB

LSB

MSB

LSB

SCK CYCLE #

(FOR REFERENCE)

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

(FROM MASTER)

MISO

(FROM SLAVE)

SS (TO SLAVE)

Table 10. Interrupt Enable (IE) Register

(MSB)(LSB)

–

ET2

ET1

EX1

ET0

EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables the interrupt.

Symbol

Position

Function

IE.7

Disables all interrupts. If EA = 0, no interrupt

is acknowledged. If EA = 1, each interrupt

source is individually enabled or disabled by

setting or clearing its enable bit.

–

IE.6

Reserved.

ET2

IE.5

Timer 2 interrupt enable bit.

IE.4

SPI and UART interrupt enable bit.

ET1

IE.3

Timer 1 interrupt enable bit.

EX1

IE.2

External interrupt 1 enable bit.

ET0

IE.1

Timer 0 interrupt enable bit.

EX0

IE.0

External interrupt 0 enable bit.

User software should never write 1s to unimplemented bits, because

they may be used in future AT89 products.

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