V54C365804VC datasheet(9/54 Pages) MOSEL

9 / 54 page

MOSEL VITELIC

V54C365804VC

V54C365804VC Rev. 0.6 September 1999

operation. If CA10 is high when a Read Command

is issued, the Read with Auto-Precharge function

is initiated. The SDRAM automatically enters the

precharge operation one clock before the last data

out for CAS latencies 2, two clocks for CAS laten-

cies 3 and three clocks for CAS latencies 4. If

CAS10 is high when a Write Command is issued,

the Write with Auto-Precharge function is initiat-

ed. The SDRAM automatically enters the precharge

operation a time delay equal to tWR (Write recovery

time) after the last data in.

Precharge Command

There is also a separate precharge command

available. When RAS and WE are low and CAS is

high at a clock timing, it triggers the precharge op-

eration. Three address bits, BA0, BA1 and A10 are

used to define banks as shown in the following list.

The precharge command can be imposed one clock

before the last data out for CAS latency = 2, two

clocks before the last data out for CAS latency = 3

and three clocks before the last data out for CAS la-

tency= 4. Writes require a time delay twr from the

last data out to apply the precharge command.

Bank Selection by Address Bits:

Burst Termination

Once a burst read or write operation has been ini-

tiated, there are several methods in which to termi-

nate the burst operation prematurely. These

methods include using another Read or Write Com-

mand to interrupt an existing burst operation, use a

Precharge Command to interrupt a burst cycle and

close the active bank, or using the Burst Stop Com-

mand to terminate the existing burst operation but

leave the bank open for future Read or Write Com-

mands to the same page of the active bank. When

interrupting a burst with another Read or Write

Command care must be taken to avoid I/O conten-

tion. The Burst Stop Command, however, has the

fewest restrictions making it the easiest method to

use when terminating a burst operation before it has

been completed. If a Burst Stop command is issued

during a burst write operation, then any residual

data from the burst write cycle will be ignored. Data

that is presented on the I/O pins before the Burst

Stop Command is registered will be written to the

memory.

A10

BA0

BA1

Bank 0

Bank 1

Bank 2

Bank 3

all Banks

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