전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

V58C2128 데이터시트(PDF) 21 Page - Mosel Vitelic, Corp

부품명 V58C2128
상세설명  HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM
PDF  59 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  MOSEL [Mosel Vitelic, Corp]
홈페이지  http://www.moselvitelic.com
Logo MOSEL - Mosel Vitelic, Corp

V58C2128 데이터시트(HTML) 21 Page - Mosel Vitelic, Corp

Back Button V58C2128 Datasheet HTML 17Page - Mosel Vitelic, Corp V58C2128 Datasheet HTML 18Page - Mosel Vitelic, Corp V58C2128 Datasheet HTML 19Page - Mosel Vitelic, Corp V58C2128 Datasheet HTML 20Page - Mosel Vitelic, Corp V58C2128 Datasheet HTML 21Page - Mosel Vitelic, Corp V58C2128 Datasheet HTML 22Page - Mosel Vitelic, Corp V58C2128 Datasheet HTML 23Page - Mosel Vitelic, Corp V58C2128 Datasheet HTML 24Page - Mosel Vitelic, Corp V58C2128 Datasheet HTML 25Page - Mosel Vitelic, Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 59 page
background image
21
MOSEL VITELIC
V58C2128(804/404/164)S
V58C2128(804/404/164)S Rev. 1.6 March 2002
Data Mask Function
The DDR SDRAM has a Data Mask function that is used in conjunction with the Write cycle, but not the
Read cycle. When the Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask
to Data Latency = 0).
When issued, the Data Mask must be referenced to both the rising and falling edges of Data Strobe.
Data Mask Timing
Burst Interruption
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by issuing a new Read command to any
bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length
starting with the new address. The data from the first Read command continues to appear on the outputs until
the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting
Read command appears on the bus. Read commands can be issued on each rising edge of the system clock.
It is illegal to interrupt a Read with autoprecharge command with a Read command.
Read Interrupted by a Read Command Timing
(CAS Latency = Any; Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
D0
D1
D2
D3
D4
D5
D6
D7
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Write
CK, CK
Command
DQS
DQ
DM
T9
tDMDQSS
tDMDQSS
tDMDQSH
tDMDQSH
(CAS Latency = 2; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
ReadB
NOP
NOP
NOP
NOP
NOP
NOP
DA0 DA1 DB0 DB1
ReadA
DB2 DB3
CK, CK
Command
DQS
DQ
T9



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com