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http://www.DigitalCoreDesign.com

are trademarks of their respective owners.

http://www.dcd.pl

Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.

SYMBOL

port0i(7:0)

port1i(7:0)

port2i(7:0)

port3i(7:0)

reset

clk

port0o(7:0)

port1o(7:0)

port2o(7:0)

port3o(7:0)

prgromdata(7:0)

prgramdata(7:0)

prgaddr(15:0)

prgdatao(7:0)

prgramwr

sfrdatai(7:0)

sfraddr(6:0)

sfrdatao(7:0)

sfroe

sfrwe

xaddr(23:0)

xdatao(7:0)

xdataz

xdatai(7:0)

ramaddr(7:0)

ramdatao(7:0)

ramwe

ramoe

ramdatai(7:0)

ready

xprgrd

xprgwr

xdatard

xdatawr

stop

pmm

iprgromsize(2:0)

iprgramsize(2:0)

BLOCK DIAGRAM

sfraddr(6:0)

sfrdatao(7:0)

sfrdatao(7:0)

sfroe

sfrwe

xaddr(23:0)

xdatao(7:0)

xdatai(7:0)

xdataz

ready

xprgrd

xprgwr

xdatard

xdatawr

ramaddr(7:0)

ramdatao(7:0)

ramdatai(7:0)

ramwe

ramoe

prgramdata(7:0)

prgromdata(7:0)

prgaddr(15:0)

prgdatao(7:0)

prgramwr

Program

memory

interface

Opcode

decoder

Internal data

memory

interface

User SFR’s

interface

External

memory

interface

Control

Unit

clk

reset

iprgromsize(2:0)

iprgramsize(2:0)

Interrupt

controller

ALU

DoCD™

Debug Unit

Power

Management

Unit

int0

int1

docddatai

docddatao

docdclk

pmm

stop

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

input

Global clock

reset

input

Global reset

port0i[7:0]

input

Port 0 input

port1i[7:0]

input

Port 1 input

port2i[7:0]

input

Port 2 input

port3i[7:0]

input

Port 3 input

iprgramsize[2:0]

input

Size of on-chip RAM CODE

iprgromsize[2:0]

input

Size of on-chip ROM CODE

prgramdata[7:0]

input

Data bus from int. RAM prog. memory

prgromdata[7:0]

input

Data bus from int. ROM prog. memory

xdatai[7:0]

input

Data bus from external memories

ready

input

External memory data ready

ramdatai[7:0]

input

Data bus from internal data memory

sfrdatai[7:0]

input

Data bus from user SFR’s

int0

input

External interrupt 0

int1

input

External interrupt 1

docddatai

input

DoCD™ data input

port0o[7:0]

output Port 0 output

port1o[7:0]

output Port 1 output

port2o[7:0]

output Port 2 output

port3o[7:0]

output Port 3 output

prgaddr[15:0]

output Internal program memory address bus