T80C5112-RKRIL datasheet(44/97 Pages) ATMEL

44 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

Figure 18. Data Transmission Format (CPHA = 0)

Figure 19. Data Transmission Format (CPHA = 1)

As shown in Figure 18, the first SCK edge is the MSB capture strobe. Therefore the Slave must begin driving its

data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must

be toggled high and then low between each byte transmitted (Figure 20).

Figure 20. CPHA/SS timing

Figure 19 shows an SPI transmission in which CPHA is Õ1Õ. In this case, the Master begins driving its MOSI pin

on the first SCK edge. Therefore the Slave uses the first SCK edge as a start transmission signal. The SS pin can

remain low between transmissions (Figure 20). This format may be preferable in systems having only one Master

and only one Slave driving the MISO data line.

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

Capture point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

567

Capture point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

Byte 1

Byte 2

Byte 3

MISO/MOSI

Master SS

Slave SS

(CPHA = 1)

Slave SS

(CPHA = 0)

T80C5112-RKRIL 데이터시트(PDF) 44 Page - ATMEL Corporation

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