Operating modes

M41ST84W

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2.3

WRITE mode

In this mode the master transmitter transmits to the M41ST84W slave receiver. Bus protocol

is shown in Figure 11. Following the START condition and slave address, a logic '0' (R/W=0)

is placed on the bus and indicates to the addressed device that word address An will follow

and is to be written to the on-chip address pointer. The data word to be written to the

memory is strobed in next and the internal address pointer is incremented to the next

memory location within the RAM on the reception of an acknowledge clock. The M41ST84W

slave receiver will send an acknowledge clock to the master transmitter after it has received

the slave address (see Figure 8 on page 14) and again after it has received the word

address and each data byte.

2.4

Data retention mode

WRITE cycles. Should the supply voltage decay, the M41ST84W will automatically deselect,

accomplished by internally inhibiting access to the clock registers. At this time, the Reset pin

attached battery supply.

Figure 18 on page 30).

For a further more detailed review of lifetime calculations, please see application note

AN1012.

Figure 11.

WRITE mode sequence

AI00591

BUS ACTIVITY:

S

P

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS