Device operation

M41T00

12/25

2.9

WRITE mode

In this mode the master transmitter transmits to the M41T00 slave receiver. Bus protocol is

shown in Figure 10. Following the START condition and slave address, a logic '0' (R/W = 0)

is placed on the bus and indicates to the addressed device that word address An will follow

and is to be written to the on-chip address pointer. The data word to be written to the

memory is strobed in next and the internal address pointer is incremented to the next

memory location within the RAM on the reception of an acknowledge clock. The M41T00

slave receiver will send an acknowledge clock to the master transmitter after it has received

the slave address and again after it has received the word address and each data byte (see

Figure 7).

Figure 10.

WRITE mode sequences

2.10

Data retention mode

WRITE cycles. Should the supply voltage decay, the M41T00 will automatically deselect,

Figure 11. Power down/up mode AC waveforms

AI00591

BUS ACTIVITY:

S

P

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

AI00596

VCC

tREC

tPD

VSO

SDA

SCL

DON'T CARE

Table 3.

RTC power down/up ac characteristics

Symbol

Min

Typ

Max

Unit

SCL and SDA at VIH before power down

0

ns

SCL and SDA at VIH after power up

10

µs

1.

2.