74LCX373

2/13

Figure 2: Input And Output Equivalent Circuit

Table 2: Pin Description

Table 3: Truth Table

X : Don’t Care

Z : High Impedance

* : Q Outputs are latched at the time when the LE input is taken

LOW.

Figure 3: Logic Diagram

This logic diagram has not be used to estimate propagation delays

PIN N°

SYMBOL

NAME AND FUNCTION

1OE

3 State Output Enable

Input (Active LOW)

2, 5, 6, 9, 12,

15, 16,19

D0 to D7

Data Inputs

3, 4, 7, 8, 13,

14, 17, 18

Q0 to Q7

3-State Outputs

11

LE

Latch Enable Input

10

GND

Ground (0V)

20

Positive Supply Voltage

INPUT

OUTPUT

OE

LE

D

Q

HXX

Z

L

L

X

NO CHANGE*

LHL

L

LH

H

H