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74LCX16373 데이터시트(PDF) 5 Page - STMicroelectronics

부품명 74LCX16373
상세설명  LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
PDF  10 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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74LCX16373 데이터시트(HTML) 5 Page - STMicroelectronics

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AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH =|tPLHm -tPLHn|, tOSHL =|tPHLm -tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) =CPD xVCC xfIN +ICC/16 (per
circuit)
Symbol
Parameter
Test Condition
Value
Unit
VCC
(V)
CL
(pF)
RL
(
Ω)
ts = tr
(ns)
-40 to 85 °C
-55 to 125 °C
Min.
Max.
Min.
Max.
tPLH tPHL
Propagation Delay
Time (Dn to Qn)
2.7
50
500
2.5
1.5
5.9
1.5
5.9
ns
3.0 to 3.6
1.5
5.4
1.5
5.4
tPLH tPHL
Propagation Delay
Time (LE to Qn)
2.7
50
500
2.5
1.5
6.4
1.5
6.4
ns
3.0 to 3.6
1.5
5.5
1.5
5.5
tPZL tPZH
Output Enable Time
to HIGH and LOW
level
2.7
50
500
2.5
1.5
6.5
1.5
6.5
ns
3.0 to 3.6
1.5
6.1
1.5
6.1
tPLZ tPHZ
Output Disable Time
from HIGH to LOW
level
2.7
50
500
2.5
1.5
6.3
1.5
6.3
ns
3.0 to 3.6
1.5
6.0
1.5
6.0
tS
Set-Up Time, HIGH
or LOW level
(DntoLE)
2.7
50
500
2.5
2.5
2.5
ns
3.0 to 3.6
2.5
2.5
th
Hold Time, HIGH or
LOW level
(DntoLE)
2.7
50
500
2.5
1.5
1.5
ns
3.0 to 3.6
1.5
1.5
tW
LE Pulse Width,
HIGH
2.7
50
500
2.5
3.0
3.0
ns
3.0 to 3.6
3.0
3.0
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
3.0 to 3.6
50
500
2.5
1.0
1.0
ns
Symbol
Parameter
Test Condition
Value
Unit
VCC
(V)
TA =25°C
Min.
Typ.
Max.
CIN
Input Capacitance
3.3
VIN = 0 to VCC
7pF
COUT
Output Capacitance
3.3
VIN = 0 to VCC
8pF
CPD
Power Dissipation Capacitance
(note 1)
3.3
fIN = 10MHz
VIN = 0 or VCC
20
pF



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