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USB6B1RL 데이터시트(PDF) 4 Page - STMicroelectronics

부품명 USB6B1RL
상세설명  Data line protection
PDF  9 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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USB6B1RL 데이터시트(HTML) 4 Page - STMicroelectronics

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Technical information
USB6B1
4/9
2
Technical information
2.1
Surge protection
The USB6B1 is optimized to perform surge protection based on the rail to rail topology.
The clamping voltage VCL can be estimated as follow:
VCL+ = VCC + VF for positive surges
VCL - = - VF for negative surges
with: VF =Vt + rd.Ip
VF = forward drop voltage, Vt = forward drop threshold voltage
Note:
The estimations do not take into account phenomena due to parasitic inductances.
2.2
How to ensure good ESD protection
While the USB6B1 provides a high immunity to ESD surge, an efficient protection depends
on the layout of the board. In the same way, with the rail to rail topology, the track from the
VCC pin to the power supply and from the GND pin to GND voltage must be as short as
possible to avoid overvoltages due to parasitic phenomena (see Figure 4.)
It’s often harder to connect the power supply near to the USB6B1 unlike the ground thanks
to the ground plane that allows a short connection. To ensure the same efficiency for
positive surges when the connections can’t be short enough, we recommend to putting a
100 nF c apacitor close to the USB6B1 between VCC and ground to prevvent these kinds of
overvoltage disturbances (see Figure 5.) The addition of this capacitor offers better
protection by providing a constant voltage during the surge.
Figure 6. shows the improvement of the ESD protection according to the recommendations
described above.
Important: An imortant precaution to take is to put the protection device closer to the disturbance
source (generally the connection).
Figure 4.
Surge behavior
Figure 5.
ESD behavior: optimized
layout and addition of a
100 nF capacitor
Lw
VI/O
ESD
SURGE
GND
I/O
+Vcc
Vf
Lw di
dt
Lw di
dt
Vcl+ = Vcc+Vf+Lw
di
dt
surge >0
-Vf- Lw
di
dt
surge <0
Vcl- =
t
tr=1ns
Vcc+Vf
Lw di
dt
Vcl+
POSITIVE
SURGE
-Lw
di
dt
t
tr=1ns
-Vf
Vcl-
NEGATIVE
SURGE
REF1=GND
VI/O
ESD
SURGE
I/O
REF2=+Vcc
C=100nF
Lw
Vcl+ = Vcc+Vf
-Vf
surge >0
surge <0
Vcl- =
t
Vcl+
POSITIVE
SURGE
t
Vcl-
NEGATIVE
SURGE



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